1. Field of the Invention
The present invention relates to a clock signal distributing system which supplies clock signals at high speed in high-speed digital apparatuses, particularly high speed computers.
2. Description of the Related Art
Heretofore, in various digital systems such as a variety of computer systems ranging from mainframe computers, supercomputers and the like to small-sized computers, synchronous operation based on clock signals is carried out. In order to carry out high-speed operation in these systems, it is required to match phases of clock signals to be supplied to a flip-flop in respective integrated circuits in a system. For this purpose, a variety of configurations have been employed. FIG. 1 is a conceptual block diagram showing a conventional clock distributing system wherein reference character CG designates a clock generating circuit, DES1 designates places to which clock signals are distributed and each of them may be, dependent upon systems, a large circuit board called back board or a circuit board simply called board, or an aggregate of integrated circuit chips called module, or an integrated circuit chip in some instances, A1 denotes amplifiers or buffer circuits for receiving clock signals, DES2 denotes further lower places to which clock signals are distributed and each of them may be a circuit board, an integrated circuit module, or an integrated circuit chip, A2 designates buffer circuits for receiving clock signals, and F designates further lower places to which clock signals are distributed. In the case where DES2 is an integrated circuit chip, A2 is a buffer circuit on the chip, and F is, for example, a final flip-flop. In actuality, such a hierarchical clock signal distributing system becomes more complicated, or conversely simpler in accordance with complexity in a system. In either case, it is necessary that a phase of clock signal is within a certain allowable (in general, considerably small) range at the position in the final circuit in a digital system.
Meanwhile, in the simplest clock signal distributing system, clock signals are delivered from the clock generating circuit CG to the final circuit F in a manner like discharging of uncontrolled effluent. In this case, the phases of clock signals which reached the final circuit F are delayed by a delay time due to the path (e.g. dependent upon the length thereof) through which the signals and by another delay time which required by an amplifier or buffer circuit through which the signals passed in comparison with the clock signals which are output immediately after the CG. A length of a signal path varies considerably dependent on the place where a final circuit resides, and a delay time in a buffer circuit also varies remarkably dependent upon individual buffer circuits. (In general, while variations in a delay time of a buffer circuit are comparatively small in the same chips, if they are different chips, the variations becomes larger.) Accordingly, such manner of delivering clock signals like discharging of uncontrolled effluent as described above is unusable except for a very small and low speed system, because of significant variations in phases of the clock signals.
In this respect, for adjusting phases of clock signals, a variety of manners have heretofore been adopted. The simplest manner is such that clock signals are observed at respective places to be distributed, for example, input points of DES1 (or output points of A1) in FIG. 1, and a suitable delay means is inserted in a clock signal line path to match the phases of clock signals. Because the phase matching is manually effected in essential in this manner, the number of places to be adjusted is limited, and the precision thereof is also not good. In these circumstances, a manner for effecting automatically phase matching has been also proposed. For instance, Japanese Patent Application No. 231516/1988 discloses a clock signal distributing system wherein a signal route for signals of phase reference is provided other than a signal route for transmitting clock signals, and as a result of referring the reference signals, phases of the clock signals are adjusted. According to this system, while phase correction is automatically carried out within a range where reference signals reach, the route for reference can be wired at placed to be distributed which are positioned only at a considerably upper part in the circuit in the hierarchical clock signal distributing system of FIG. 1. More specifically, phase adjustment by means of a reference signal is extremely difficult in a comparatively small circuit board or an integrated circuit chip. Thus, it is required to adjust phases by regulating a length of wiring and the like (e.g. each length of wiring up to the place to be distributed is made equal to each other, in other words, a so-called equivalent length wiring is applied) with respect to the places to be distributed which are positioned at the lower part of the circuit than that where the route for phase reference is positioned. However, when equivalent length wiring is applied to all the places to be distributed, increase in the chip area therefor becomes remarkable so that this is disadvantage from a viewpoint of costs. Furthermore, increase in resistance of wiring on chips becomes remarkable with elevation of a degree of integration in an integrated circuit, so that variations in delay time due to CR increase. Thus, it becomes very difficult to match phases of clock signals by means of equivalent length wiring.
Moreover, a clock signal distributing system which is attained from another approach and provides clock signals having extremely low phase difference has also been proposed. Such a signal distributing system that excitation signals (clock signals) with respect to quantum flux parametron at cryogenic temperatures are supplied as standing wave on a transmission line path made of superconductor is described, for example, in RIKAGAKU KENKYUJO Symposium "Josephson Electronics" (Mar. 16, 1984), Collection of preliminary Theses, pp. 48-51; and "Quantum Flux Parametron Shift Registers Clocked by an Inductive Power Distribution Network and Errorless Operation of the QFP", IEEE Trans Applied Superconductivity, Vol. 2, No. 1, pp. 26-32, March 1992. In this case, since the transmission path is composed of a superconductor, it is not required to consider attenuation in signals due to resistance and a phase lag due to CR and the like. However, in operation at room temperature, particularly on, for example, high integrated semiconductor chips, resistance in wiring becomes very high as mentioned above, so that rotation of phase and attenuation in signals become very remarkable. Hence, this clock signal distributing system by means of standing wave is not practically used without any modification.
As described above, it is absolutely impossible to use for the adjustment of phases up to the places to be distributed at the terminals in a system, and further phase matching by means of equivalent length wiring is also impossible from physical and practical points of view.